For almost as long as this website has been existence, there has been ample speculation and concern over the future of Moore’s Law. The observation, penned by Intel’s co-founded Gordon Moore, has to date correctly predicted the driving force behind the rapid growth of the electronics industry, with massive increases in transistor counts enabling faster and faster processors over the generations.
The heart of Moore’s Law, that transistor counts will continue to increase, is for the foreseeable future still alive and well, with plans for transistors reaching out to 7nm and beyond. However in the interim there is greater concern over whether the pace of Moore’s Law is sustainable and whether fabs can continue to develop smaller processes every two years as they have for so many years in the past.
The challenge facing semiconductor fabs is that the complexity of the task – consistently etching into silicon at smaller and smaller scales – increases with every new node, and trivial physics issues at larger nodes have become serious issues at smaller nodes. This in turn continues to drive up the costs of developing the next generation of semiconductor fabs, and even that is predicated on the physics issues being resolved in a timely manner. No other industry is tasked with breaking the laws of physics every two years, and over the years the semiconductor industry has been increasingly whittled down as firms have been pushed out by the technical and financial hurdles in keeping up with the traditional front-runners.
The biggest front runner in turn is of course Intel, who has for many years now been at the forefront of semiconductor development, and by-and-large the bellwether for the semiconductor fabrication industry as a whole. So when Intel speaks up on the challenges they face, others listen, and this was definitely the case for yesterday’s Intel earnings announcement.
As part of their call, Intel has announced that they have pushed back their schedule for the deployment of their 10nm process, and in turn it has affected their product development roadmap. Acknowledging that the traditional two year cadence has become (at best) a two and a half year cadence for Intel, the company’s 10nm process, originally scheduled to go into volume production in late 2016, is now scheduled to reach volume production in the second half of 2017, a delay of near a year. This delay means that Intel’s current 14nm node will in effect become a three year node for the company, with 10nm not entering volume production until almost three years after 14nm hit the same point in 2014.
Svi koji smo u IT-u znamo za otrcanu frazu koja se ponavljala svake godine, da dolazi kraj Murovom "zakonu". Mnogo puta ponovljeno "prorocanstvo" je bilo opovrgnuto bezbroj puta do sad tako da je cela fraza potala potpuno izlizana do sad.
Medjutim, uprkos svim unapredjenjima koja su dolazila "k'o porucena" vec nekoliko decenija u nazad, svima je uvek bilo jasno da ce zakoni fizike pre ili kasnije morati da uspore trend dupliranja broja tranzistora po jedinici povrsine. Intel, IBM, Samsung i ekipa su do sada uspesno uspevali da odrze trend uprkos mnogobrojnim problemima koji su resavani "u letu" kako su procesi proizvodnje opadali sa 1 mikrona na svega 14 nanomentra.
Medjutim Intel-ovo prvo vece kasnjenje sa 14nm procesom je mozda bio prvi znak buducnosti koja dolazi - do danasnjeg deljenja informacija sa investitorima su se polagale nade da je 14nm kasnjenje koje je izazvalo poprilicno veliku promenu u proizvodima (eliminacija Broadwell desktop procesora npr.) samo "glitch". Sada je ta nada zakopana - jasno je da ce problemi postajati sve veci i da ce 10nm proces doci sa zagasnjenjem od bar jedne godine.
Naravno, Moore-ov "zakon" u svojoj originalnoj formulaciji ce vrlo verovatno izdrzati jos malo uz pomoc utabanih evolucija fabrikacije i probijanja 10nm barijere jos koji put, ali bez nekih revolucionarnih promena u procesu fabrikacije je izvesno da ce industrija morati da nadje neke druge nacine pojeftinjenja cene po tranzistoru izmedju generacija umesto dosadasnjeg smanjenja velicine tranzistora.