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Sepa011

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^{21.07.2011. u 18:41 - pre 155 meseci}

Nece biti da 16F628(A) ima OSCCON trgistar

Ovo su ti svi registri doticnog piconje:

Code:
SFR Definitions
[REGSTART]
INDF EQU 0X0000
TMR0 EQU 0X0001
PCL EQU 0X0002
STATUS EQU 0X0003
FSR EQU 0X0004
PORTA EQU 0X0005
PORTB EQU 0X0006
PCLATH EQU 0X000A
INTCON EQU 0X000B
PIR1 EQU 0X000C
TMR1L EQU 0X000E
TMR1LH EQU 0X000F
TMR1H EQU 0X000F
T1CON EQU 0X0010
TMR2 EQU 0X0011
T2CON EQU 0X0012
CCPR1L EQU 0X0015
CCPR1LH EQU 0X0016
CCPR1H EQU 0X0016
CCP1CON EQU 0X0017
RCSTA EQU 0X0018
TXREG EQU 0X0019
RCREG EQU 0X001A
CMCON EQU 0X001F
OPTION_REG EQU 0X0081
TRISA EQU 0X0085
TRISB EQU 0X0086
PIE1 EQU 0X008C
PCON EQU 0X008E
PR2 EQU 0X0092
TXSTA EQU 0X0098
SPBRG EQU 0X0099
EEDATL EQU 0X009A
EEDATA EQU 0X009A
EEDAT EQU 0X009A
EEADR EQU 0X009B
EECON1 EQU 0X009C
EECON2 EQU 0X009D
VRCON EQU 0X009F
[REGEND]

Vrsta oscilaora se bira preko konfiguracione reci:

Code:
REGISTER 14-1: CONFIGURATION WORD
CP1 CP0 CP1 CP0 — CPD LVP BODEN MCLRE FOSC2 PWRTE WDTE F0SC1 F0SC0
bit 13 bit 0
bit 13-10: CP1:CP0: Code Protection bits (2)
Code protection for 2K program memory
11 = Program memory code protection off
10 = 0400h-07FFh code protected
01 = 0200h-07FFh code protected
00 = 0000h-07FFhcode protected
Code protection for 1K program memory
11 = Program memory code protection off
10 = Program memory code protection off
01 = 0200h-03FFh code protected
00 = 0000h-03FFh code protected
bit 9: Unimplemented: Read as ‘0’
bit 8: CPD: Data Code Protection bit
(3)
1 = Data memory code protection off
0 = Data memory code protected
bit 7: LVP: Low Voltage Programming Enable
1 = RB4/PGM pin has PGM function, low voltage programming enabled
0 = RB4/PGM is digital I/O, HV on MCLR must be used for programming
bit 6: BODEN: Brown-out Detect Reset Enable bit
(1)
1 = BOD Reset enabled
0 = BOD Reset disabled
bit 5: MCLRE: RA5/MCLR pin function select
1 = RA5/MCLR pin function is MCLR
0 = RA5/MCLR pin function is digital Input, MCLR internally tied to VDD
bit 3: PWRTEN: Power-up Timer Enable bit
(1)
1 = PWRT disabled
0 = PWRT enabled
bit 2: WDTEN: Watchdog Timer Enable bit
1 = WDT enabled
0 = WDT disabled
bit 4, 1-0: FOSC2:FOSC0: Oscillator Selection bits(4)
111 = ER oscillator: CLKOUT function on RA6/OSC2/CLKOUT pin, Resistor on RA7/OSC1/CLKIN
110 = ER oscillator: I/O function on RA6/OSC2/CLKOUT pin, Resistor on RA7/OSC1/CLKIN
101 = INTRC oscillator: CLKOUT function on RA6/OSC2/CLKOUT pin, I/O function on RA7/OSC1/CLKIN
100 = INTRC oscillator: I/O function on RA6/OSC2/CLKOUT pin, I/O function on RA7/OSC1/CLKIN
011 = EC: I/O function on RA6/OSC2/CLKOUT pin, CLKIN on RA7/OSC1/CLKIN
010 = HS oscillator: High speed crystal/resonator on RA6/OSC2/CLKOUT and RA7/OSC1/CLKIN
001 = XT oscillator: Crystal/resonator on RA6/OSC2/CLKOUT and RA7/OSC1/CLKIN
000 = LP oscillator: Low power crystal on RA6/OSC2/CLKOUT and RA7/OSC1/CLKIN
Note 1: Enabling Brown-out Detect Reset automatically enables Power-up Timer (PWRT) regardless of the value of bit PWRTE.
Ensure the Power-up Timer is enabled anytime Brown-out Detect Reset is enabled.
2: All of the CP1:CP0 pairs have to be given the same value to enable the code protection scheme listed.
3: The entire data EEPROM will be erased when the code protection is turned off.
4: When MCLR is asserted in INTRC or ER mode, the internal clock oscillator is disabled.
Legend
R = Readable bit W = Writable bit U = Unimplemented bit, read as ‘0’
-n = Value at POR 1 = bit is set 0 = bit is cleared x = bit is unknown

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