Imam sledeci problem:
Imam zadatak da umjesro sensitivity list u processu stavim WAIT Klauze.
implementirao sam zadatak na sledeci nacin
ali kad pokusam da napravim RTL shematic ili Test Bench javi mi sledecu poruku
Bad condition in wait statement, or only one clock per process
sta nije u redu sa uslovom u wait?
Imam zadatak da umjesro sensitivity list u processu stavim WAIT Klauze.
implementirao sam zadatak na sledeci nacin
Code:
entity Mux41 is
port( x0, x1, x2, x3: in std_logic;
sel: in std_logic_vector(1 downto 0);
y: out std_logic);
end Mux41;
architecture Behavioral of Mux41 is
begin
process
begin
wait on sel, x0, x1, x2, x3;
case sel is
when "00" => y<= x0;
when "01" => y<= x1;
when "10" => y<= x2;
when others => y<= x3;
end case;
end process;
end Behavioral;
entity Mux41 is
port( x0, x1, x2, x3: in std_logic;
sel: in std_logic_vector(1 downto 0);
y: out std_logic);
end Mux41;
architecture Behavioral of Mux41 is
begin
process
begin
wait on sel, x0, x1, x2, x3;
case sel is
when "00" => y<= x0;
when "01" => y<= x1;
when "10" => y<= x2;
when others => y<= x3;
end case;
end process;
end Behavioral;
ali kad pokusam da napravim RTL shematic ili Test Bench javi mi sledecu poruku
Bad condition in wait statement, or only one clock per process
sta nije u redu sa uslovom u wait?
Potpis
Apartmani na Jahorini http://www.apartmanimaja.com